1. Field of the Invention
The present invention relates generally to dynamic semiconductor memory devices having a multi-bit configuration as a unit and image data generation device for generating image data of a selected number of bits, and more particularly, to memory devices enabling selective read of a specified smaller number of bits out of a given larger plurality of bits.
2. Description of the Background Art
A conventional dynamic random access memory device (hereinafter referred to as DRAM) generates data by 1 bit, 4 bits or 8 bits. DRAM devices of .times.4 bits and .times.8 bits are generally called memory devices having a multi-bit configuration.
In the field of image processing, data is often used on an basis such as 6 bits or 7 bits. This is because of the following reason. That is, memories are originally used in computers to store 4-bit, 8-bit or 16-bit data. On the other hand, 6-bit or 7-bit data is used for image processing. While a 8-bit memory has a large memory capacity, it incurs more expensive manufacturing costs, and production of special 6-bit or 7-bit memories also costs much.
Such image data of 6-bit or 7-bit is used for forming such special images as those in a search mode and slow reproduction (see "Home VTR Containing Field Memory for Correcting Crossbar and Skew Distortion in Search Mode" NIKKEI ELECTRONICS, Oct. 20, 1986, Vol. 406).
FIG. 12A is a block diagram showing a device for generating 6-bit luminance data shown in the above-described article.
With reference to FIG. 12A the device includes .times.4-bit memory devices M1, M2 and M3 and a selector 50 for selecting 6-bit data. Luminance data is written in each of memory devices M1-M3 by 4 bits. Selector 50 alternately selects either 4-bit data from memory device M1 and 2-bit data from memory device M3 or 2-bit data from memory device M3 and 4-bit data from memory device M2 for each field. 6-bit luminance data is generated at the output terminal of selector 50 in this way.
Selector 50, however, requires 6 switch circuits for selecting 6-bit data, which necessitates an increased number of elements.
The memory device in FIG. 12A is considered to have the structure as shown in FIGS. 12B to 12D.
FIG. 12B is a block diagram of a DRAM having 4-bit configuration. FIG. 12C is a timing chart of the DRAM device of FIG. 12B.
With reference to FIG. 12B, the DRAM device comprises an RAS terminal for receiving a row address strobe signal RAS (hereinafter referred to as an RAS signal), a CAS terminal for receiving a column address strobe signal CAS (hereinafter referred to as a CAS signal), Add terminals for receiving an address signal Add, an OE terminal for receiving an output enable signal OE, data input/output terminals DQ1-DQ4 and a WE terminal for receiving a write control signal WE. Data input/output terminals DQ1-DQ4 receive input/output data.
The DRAM device further includes a memory cell array 1, a row decoder 2, a column decoder 3, an address buffer 4, an RAS buffer 5, a CAS buffer 6, an output buffer 7, an input buffer 8, a OE buffer circuit 90 and a WE buffer circuit 100.
Memory cell array 1 is divided into four memory cell array blocks 1a, 1b, 1c and 1d. A plurality of memory cells MC arranged in a matrix, word lines WL arranged in a row direction and bit lines BL arranged in a column direction are provided in each of memory cell array blocks 1a-1d. Row decoder 2 decodes a row address signal of an address signal applied in a time divisional manner to select one word line WL of each of memory cell array blocks 1a-1d. Column decoder 3 decodes a column address signal of an address signal applied in a time divisional manner to select one (a pair of bit lines) bit line BL of each of memory cell array blocks 1a-1d. As a result, a memory cell at the word line and the bit line selected by row decoder 2 and column decoder 3 is simultaneously designated in each of memory cell array blocks 1a-1d.
Address buffer 4 receives address signal Add to generate an internal address signal. The internal address signal is applied to row decoder 2 and column decoder 3.
RAS buffer 5 receives row address strobe signal RAS to generate an internal RAS signal. The internal RAS signal is applied to row decoder 2 and 0E buffer circuit 90.
CAS buffer 6 receives CAS signal to generate an internal CAS signal. The internal CAS signal is applied to column decoder 3.
OE buffer circuit 90 is coupled to output buffer 7 in a differential manner and connected to OE terminal data. OE buffer circuit 90 activates output buffer 7 in response to OE signal.
WE buffer circuit 100 is coupled to input buffer 8 in a differential manner and connected to WE terminal. WE buffer circuit 100 activates input buffer 8 in response to write enable signal WE.
Output buffer 7 receives data from memory cells of 4 bits and applies the received data to data input/output terminals DQ1-DQ4.
Input buffer 8 receives the 4-bit data from data input/output terminals DQ1-DQ4 and applies the same to designated memory cells of 4 bits.
FIG. 12C is a timing chart illustrating an operation of the DRAM device of FIG. 12B. The hatched portions of the drawing are in an arbitrary state.
A row address signal included in an address signal Add is strobed at a fall of RAS signal and a column address signal is strobed at a fall of CAS signal. A row address and a column address designate a memory cell in the memory cell array. The data from the input/output terminal DQ1-DQ4 is written at the designated memory cells, and the written data is read out from the memory cells.
FIG. 12D is a block diagram showing the output buffer of FIG. 12B. With reference to the figure, output buffer 7 includes data output buffers 71, 72, 73 and 74.
Each of data output buffers 71-74 is connected between the corresponding data input/output terminal DQ1-DQ4 and an I/O terminal of memory cell array 1 and enters a read allowed state or a read inhibited state (high impedance state) in response to the OE signal.
A common DRAM having a multi-bit configuration includes an output enable terminal, to which terminal an output enable signal OE (hereinafter referred to as 0E signal) is applied, thereby simplifying the structure of the image data generation device.
FIG. 13 is a block diagram showing an image data generation device using an OE signal. With reference to FIG. 13, the image data generation device includes data input/output terminals DQ1, DQ2, DQ3 and DQ4, memory devices M1, M2, and M3 of .times.4-bit configuration, a timing generator 51 and a selector 52.
Timing generator 51 generates output enable signals OE1 and OE2 and a selection signal .phi. in response to a clock signal .phi.. OE1 signal and OE2 signal are applied to memory devices M1 and M2, respectively, and .phi. signal is applied to selector 52.
Memory device M1 comprises output ports 1a, 1b, 1c and 1d, memory device M2 comprises output ports 2a, 2b, 2c and 2d and memory device M3 comprises output ports 3a, 3b, 3c and 3d. Output ports 1a-1d and 2a-2d are connected to data output terminals DQ1-DQ4, while output ports 3a-3d are connected to input terminals of selector 52. Selector 52 includes 2-input 1-output switch circuits 52a and 52b. Switch circuit 52a has input terminals connected to output ports 3a and 3b and an output terminal connected to a data input/output terminal DQ5. Switch circuit 52b has input terminals connected to output ports 3c and 3d and an output terminal connected to a data input/output terminal DQ6.
FIG. 14 is a timing chart of the image data generation device of FIG. 13. Memory device M1 outputs data when OE1 signal is at a low level, while memory device M2 outputs data when OE2 signal is at a low level. Memory device M3 outputs data at any time because 0E signal is fixed to a ground level. Selector 52 selects output ports 3a and 3c when .PHI. signal is at a low level and selects output ports 3b and 3d when .PHI. signal is at a high level. Data input/output terminals DQ1-DQ4 alternately receive 4-bit data from memory device M1 and 4-bit data from memory device M2, while data output terminals DQ5 and DQ6 alternately receive 2-bit data (3a-3c) and (3b, 3d) out of 4-bit data generated from memory device M3. Data input/output terminals DQ1-DQ6 obtain 6-bit data in this way.
Extremely high speed data processing is desirable in the field of the image processing.
However, an image data generation device should include selectors provided outside memory devices as shown in FIGS. 12A and 13 such that data read from the memory devices is output through interconnections and the selectors. Data transmission speed is reduced as a result. In addition, four data lines of each memory device are connected to inputs of each selector, making the interconnections complicated.
The present invention is directed to selectively inhibiting the memory device of FIGS. 13 and 14 from outputting a specified bit in order to avoid the necessity of a selector.
Such a memory device has not yet been producted.